Products

Industry's Most Powerful DSP Platform

SPI's Storm-1 stream processors provide embedded system designers with a whole new level of development cost savings without having to sacrifice performance.

A comprehensive development environment consists of standards-based ANSI C software tools, development kits, and reference design kits.

To help jump-start your projects, software training is available, and SPI's third party partner ecosystem is supporting with everything from turn-key products to algorithms and DSP programming.

Not Your Mother's DSP

Storm-1 and stream processing represents a significant step in the evolution of DSP and processor technology. The architecture was defined with the programmer in mind to eliminate the programming complexities of traditional DSPs and multicore, and yet deliver highly scalable, power-efficient compute power at low cost.

Main attributes include:

Performance and scalability: Stream processing provides a bandwidth-efficient, scalable architecture that leverages the data-parallelism in embedded applications. The first generation Storm devices provides up to 224,000 MMACs, which is more than an order of magnitude higher performance than traditional DSPs.

Ease of use: SPI's optimizing C compiler stages data movement and on-chip memory usage for a predictable, linear development flow. Libraries and Linux-based system framework allows for a higher level of abstraction.

Flexibility: SPI's stream processors ensure flexibility through full software programmability. In contrast, traditional DSPs have lately been adding hardware blocks with limited flexibility.

Power-efficiency: Stream processing is inherently power-efficient due to a distributed memory hierarchy and a data-parallel execution. The Storm-1 series delivers 5.0-8.0 MMAC/mW of compute efficiency, significantly better than traditional DSPs and x86 type processors.

Cost-efficiency: Cost-efficiency for processors can roughly be measured by looking at the MMAC/mm2 metric, development effort and amount of software reuse. The stream processor architecture is compact due to data-parallelism and reduced need for large caches, while development is simplified due to available compute headroom and sophisticated C tools.

Data-parallel operation vs. thread-parallel: For real-time applications, operating on chunks of data in parallel with one program flow, is generally more efficient than running several threads in parallel. SPI's stream processor is optimized to exploit this data-parallelism, eliminating the system overhead of synchronizing and load-balancing individual cores.