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Storm-1 Series Benchmarks
Below is a sample of a few representative benchmarks. For further information, including source code and other benchmarks, please contact SPI.
| Storm-1 Series Performance Metrics |
|---|
| Metric | Storm-1 SP16HP-G220 | | Frequency | DPU: 16 lanes, 700 MHz, 2 x MIPS 4KEc: 330 MHz | | Performance (peak multiply-add) | 224 GMACS (8x8-bit) / 112 GMACS (16x16-bit) | | Performance (peak logic operations) | 448 GOPS (8-bit) / 224 GOPS (16-bit) | | Energy Efficiency | <100 µW/MMAC (16-bit) | | Sample Benchmark | Data | | 8 x 8 Forward DCT | 5.94 cycles/8x8 block, 118 Mblocks/s (IEEE 1180 compliant) | | 16 x 16 SAD | 4.68 cycles/16x16 block, 38 GSADS/s | | RGB to YUV Color Space Conversion | 0.36 cycles/sample, 1938 Msamples/s (RGB sample, 16-bit math) | | 3 x 3 Convolution Filter | 0.13 cycles/pixel, 5.06 Gpixels/s (8-bit pixel, 8-bit coefficient) | | 5 x 5 Convolution Filter | 0.33 cycles/pixel, 2.12 Gpixels/s (8-bit pixel, 16-bit coefficient) | | Floyd-Steinberg Error Diffusion | 1.07 cycles/pixel, 647 Mpixels/s (16-bit math) | | H.264 BP Encoder | HD: 720p60 / 1080p30, D1: 180 fps (6 channels) | | MIMO MMSE Receiver for LTE/WiMax | 0.05 cycles/bit, 14 Gbps |
Results from compiled C code using RapiDev Tools Suite Version 1.0.3 running on Storm-1 Development Kit
Metrics for other Storm-1 Series members can be estimated by scaling clock frequency and number of lanes (8 or 16). | DSP Industry Comparisons¹ |
|---|
| Manufacturer | SPI | TI | Xilinx | Altera | | Device Type | Storm-1
SP16HP-G220 | DaVinci
TMS320DM6467 | Virtex-5
5VSX35T | Stratix III
EP3SL70 | | Architecture | SIMD VLIW DSP:
Stream Processor | VLIW DSP +
HW accel: | FPGA | FPGA | | Clock Frequency | 700 MHz | 729 MHz | 5 50 MHz | 300 MHz | | GMACS | 112 | 2.9 | 106 | 86 | Devices for ~100 GMACS
of compute performance | 1 | 34 | 1 | 1 | | Design Methodology | C programming | C programming | Hardware-oriented
(VHDL, Verilog) | Hardware-oriented
(VHDL, Verilog) |
¹ Source: Company websites and other officially published material
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