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Storm-1 Series >
Selection Guide
| Storm-1 Selection Guide |
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Device
| SP8LP-G30
| SP8-G80
 | SP16-G160
 | SP16HP-G220
 | | Status | Volume production | Volume production | Volume production | Volume production | | System CPU | MIPS 4KEc, 200 MHz | MIPS 4KEc, 280 MHz | MIPS 4KEc, 280 MHz | MIPS 4KEc, 330 MHz | | DSP Subsystem | 8 lanes¹, 200 MHz
MIPS 4KEc, 200 MHz | 8 lanes¹, 500 MHz
MIPS 4KEc, 280 MHz | 16 lanes¹, 500 MHz
MIPS 4KEc, 280 MHz | 16 lanes¹, 700 MHz
MIPS 4KEc, 330 MHz | | DSP Performance | 32 GMACS
320 ops/cycle | 80 GMACS
320 ops/cycle | 160 GMACS
640 ops/cycle | 224 GMACS
640 ops/cycle | | Memory Interface | 16-/32-bit DDR1/DDR2, 466 MHz data rate
8-bit PIO Flash/SRAM | 16-/32-/64-/128-bit DDR1/DDR2, 466 MHz data rate
8-bit PIO Flash/SRAM | 16-/32-/64-/128-bit DDR1/DDR2, 466 MHz data rate
8-bit PIO Flash/SRAM | 16-/32-/64-/128-bit DDR1/DDR2, 666 MHz data rate
8-bit PIO Flash/SRAM | StreamI/O™
| 36 configurable I/O pins for SD/HD video, sensor and raw data | 108 configurable I/O pins for SD/HD video, sensor and raw data | 108 configurable I/O pins for SD/HD video, sensor and raw data | 108 configurable I/O pins for SD/HD video, sensor and raw data | | Ethernet | 10/100 MII | 10/100/1000 GMII/MII | 10/100/1000 GMII/MII | 10/100/1000 GMII/MII | | PCI | 33 MHz, 32-bit, PCI 2.2, master/agent | 33/66 MHz, 32-bit, PCI 2.2, master/agent | 33/66 MHz, 32-bit, PCI 2.2, master/agent | 33/66 MHz, 32-bit, PCI 2.2, master/agent | | General I/O | 3 x I²S, I²C,
SPI/SSP/Micro-
wire, 2 x UARTs,
32-pin GPIO (muxed) | 9 x I²S, 4 x I²C,
2 x SPI/SSP/Micro-
wire, 3 x UARTs,
64-pin GPIO (muxed) | 9 x I²S, 4 x I²C,
2 x SPI/SSP/Micro-
wire, 3 x UARTs,
64-pin GPIO (muxed) | 9 x I²S, 4 x I²C,
2 x SPI/SSP/Micro-
wire, 3 x UARTs,
64-pin GPIO (muxed) | | Package | 480-pin, 23x23mm
PBGA, 1.0 mm pitch | 896-pin, 31x31mm
HSBGA, 1.0 mm pitch | 896-pin, 31x31mm
HSBGA, 1.0 mm pitch | 896-pin, 31x31mm
FCBGA, 1.0 mm pitch | | Environ-mental | Green, Pb-free
RoHS compliant | Green, Pb-free
RoHS compliant | Green, Pb-free
RoHS compliant | Green, Pb-free
RoHS compliant |
¹ Each lane is a 15-stage, 12-way VLIW core with five 32-bit ALUs capable of twenty 8-bit operations/cycle including MACs
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